Integrated circuit chips today have up to 774 million transistors and have a die size of 296 mm2. With such complexity of designs, and the number of transistors that need to be “placed and routed” (in industry terms), the wires that connect the transistors are becoming increasingly complex and small. As wires have gotten smaller, they have or are about to reach the limits of physics.
On-chip interconnects have been a rising area of concern to the IC chip industry as interconnects have increased in resistance and capacitance, leading to timing issues and higher power consumption by the interconnects. Nearly half the power consumed by an average computer is spent on the interconnects!This is because as the transistors have gotten smaller, the wires connecting them have also gotten smaller, but without help, the tiny signals from each transistor are not strong enough to make it across even the tiniest wires. Another structure, called a repeater or a buffer, is needed to strengthen the signal.
When playing with large components like connecting wires and light bulbs to batteries, the wire was thought to be an equipotential region throughout the wire and also the voltage and current change was instantaneous. Wires are considered ideal when the circuits are designed for functionality like converting mp3 data bits into music. In the implementation of functions via actual IC circuits, however, the reality is that dimensions of current IC wires (interconnects) are so small that parasitic capacitance and resistance, properties of their geometry, material properties and the surrounding material, become so complex on the scale that they cannot be ignored and become significant design challenges.
When the cross sectional area of wires became small enough that their resistance increased immensely and yet their lengths did not scale as much, then the resistance and capacitance due to the wire could no longer be ignored. They were termed parasitic resistance and capacitance and contributed to the delay of the signal propagation along the wires.
Ultimately, since interconnects on VLSI chips are the material media where currents and charge are moving in, then in general it also follows electromagnetic laws. However transmission line effects come into play when wavelengths of the signal are comparable to the dimensions or length of the wires. Then at those times it cannot be assumed that the voltage and current are the same along the length of the wire, but instead they propagate like a wave down the wire. These effects are particularly evident when switching times are increasingly fast and the inductance dominates the delay behavior, especially when resistance is low, like on global metal lines which are much wider. Then interconnects behavior follow the transmission line equations (or telegrapher's equations):
                    ∂                  V          ⁡                      (            x            )                                      ∂        x              =                            -                      (                          R              +                              j                ⁢                                                                  ⁢                ω                ⁢                                                                  ⁢                L                                      )                          ⁢                  I          ⁡                      (            x            )                          ⁢                                  ⁢        and        ⁢                                  ⁢                              ∂                          I              ⁡                              (                x                )                                                          ∂            x                              =                        -                      (                          G              +                              j                ⁢                                                                  ⁢                ω                ⁢                                                                  ⁢                C                                      )                          ⁢                  V          ⁡                      (            x            )                                ⁢        and combined they make:
                              ∂          2                ⁢                  V          ⁡                      (            x            )                                      ∂                  x          2                      =                            Γ          2                ⁢                  V          ⁡                      (            x            )                          ⁢                                  ⁢        or        ⁢                                  ⁢                                            ∂              2                        ⁢                          I              ⁡                              (                x                )                                                          ∂                          x              2                                          =                        Γ          2                ⁢                  I          ⁡                      (            x            )                                ⁢        withΓ=√{square root over ((R+jωL)(G+jωC))}{square root over ((R+jωL)(G+jωC))}and the characteristic impedance is:
      Z    0    =                    R        +                  j          ⁢                                          ⁢          ω          ⁢                                          ⁢          L                            G        +                  j          ⁢                                          ⁢          ω          ⁢                                          ⁢          C                    
Characteristic impedance is the ratio of the instantaneous voltage and current at a point on the wire. If there are discontinuities in the characteristic impedance on any point of the wire, then signal reflections could occur and cause signal integrity issues and power transfer issues.
Transmission lines are typically divided into two low-loss lines and lossy lines, where low-loss lines have negligible resistance and conductance (G), and in lossy lines the resistance and conductance cannot be neglected. Most dielectric materials used in IC chip manufacturing are insulators, the conductance is very low since they are insulators, except for cases when water vapor is introduced into the dielectrics. And also when resistance is very high, inductance is comparatively low at that frequency, the circuits are then dominated by the RC effects and not the LC effects.
As the wires increase in width, the resistance goes down, and global wires typically have less resistance per unit length. Actual total resistance values for M1-M3 wires are scaled by their length, so for M1-M3 wires which are much shorter, for lengths of around 1 gate pitch (now typically the same as the M1 pitch), the total actual resistance value is much less.
Resistivity is also influenced by geometry when electrons are now also encountering the boundaries of the conductor in their mean free path due to the much smaller dimensions of the conductor. Resistance used to be calculated just by the bulk resistivity, which is 1.7 μΩ-cm for copper.
Also another issue with resistance is with the use of copper interconnects, since the dual damascene process had to be implemented, barrier metals like cobalt, titanium, titanium nitride, tantalum, tantalum nitride are used to prevent copper ions from diffusing into the silicon dioxide or silicon and degrade the insulation of the dielectric. The barrier metals typically have good conductivity but the resistivity of the metals is still higher than copper, like tantalum has a resistivity 10 times higher than copper and so increases the resistivity of the interconnect.
Also at higher frequencies, the resistance increases as the current does not tend to flow uniformly through the whole conductor, but instead flow on the surface which reduces the total surface area. This is expected to be an issue for larger wires, which at the frequencies used are much larger than the skin depth so the effective surface area is reduced. On the M1 and intermediate wires or minimum global pitch the skin depth is as wide as the wire, and so does not have an effect. The equation for skin depth is:
  δ  =            ρ              π        ⁢                                  ⁢        f        ⁢                                  ⁢        μ            Copper at 1 Ghz has a skin depth of 2 um.
Inductance (self-inductance) is also calculated from the geometry of the conductor and its distances to other inductors. Self-inductance is generally negligible because most materials used in IC chip manufacturing have a magnetic permeability of vacuum. Mutual inductance depends highly on the current return path. Mutual inductance describes the inductive coupling that will be seen degrading signals. The current return paths are not set and the current will return on the paths that have the lowest impedance (Z=R+jwL). In VLSI logic design, data paths are connected to the gate port of the CMOS and so are terminated by capacitors. Current can also return on adjacent wires, parallel power supply buses, or the substrate. Therefore typically at lower frequencies global signal lines which have much lower resistances will have the lowest impedance and will be the sources of the current return. At higher frequencies, however, the lower impedance return paths may be on smaller signal wires, which may be closer to each other. So therefore the area of the influence of the magnetic flux generated by that loop that couples to the other loops of wires may increase or decrease along with the change of frequency.
Inductance, L, is also multiplied by the frequency in the impedance, jwL, so at higher frequencies the inductance increases. The wire can no longer be considered in the RC regime, but modeled as a transmission line if the time of flight, length divided by the propagation velocity, is longer than the rise time of the driving transistor, which is expressed as:
      t    r    <      2.5    ⁢          L              v        p            
Loss is generally not an issue for on-chip interconnects because the length of the majority of wires is too short. It is not the loss limiting the clock speed, rather than it is the RC delay that limits the clock speed.
The loss tangent is generally calculated with this equation:
      tan    ⁢                  ⁢    δ    =                    ωε        ″            +      σ              ωε      ′      but ignoring the imaginary part of the dielectric constant the loss tangent is calculated for transmission lines as:
      tan    ⁢                  ⁢    δ    =            ESR                                X          c                              =                  ω        ⁢                                  ⁢                  C          ·          ESR                    =              σ                              ε            ′                    ⁢          ω                    
Silicon dioxide is an insulator and has a very low conductivity of 10−9 to 10−16 S/cm (varies with what process the silicon dioxide is made and its impurities, for films on doped silicon, the conductivity is higher), which brings its loss tangent per GHz (using keff=4.2 for silicon dioxide and the highest conductivity 10−9) to be: 4.28×10−11 which is still very much less than 1 and the dielectric is considered low loss.
For low loss tangents (<<1), tan δ≈δ, then power attenuation would be characterized by:P=Poe−δkz Meaning the length at which it attenuates to e−1 level, is 1/δk, which for silicon dioxide is 4.85×1011 m.
Compared with FR4, which has a conductivity that is largely frequency dependent so that at 1 Ghz the conductivity is 10−4 S/cm, the loss tangent is much higher. FR4 has a transition frequency at 10 Hz at which the conductivity goes up much higher.
Porous silicon dioxide materials can be expected to be even further insulating because of the inclusion of air pockets and so would also have lower conductivities, and thus lower loss tangents.
Conductance is also a measure of the dielectric loss of a material and for the parallel plate or microstrip configuration of the conductors on the IC chip. Some attempts at measuring the permittivity of low-k materials have also tried to measure the conductance but it was found that the metal loss greatly exceeds the dielectric loss, even at frequencies of 40 Ghz.
RC Delay calculated from the resistance and capacitance of the element is the measure of an element to discharge to 37% of its original charge. With interconnects, resistance and capacitance are modeled as lumped or distributed resistances and capacitances because the majority of the wire lengths inside of a chip are still much shorter than the signal wavelength and transmission line models are not needed. Therefore most of the wires on the IC chip are RC limited, and some wires may have some transmission line effects, particularly the global wires that are much longer.
RC delay in general prevents clocks and data from switching as fast and limits your clock speed. However since resistance and capacitance is dependent on the length of the wire, for shorter lengths, RC delay is very small. For longer wires like the global interconnects, RC delay becomes as much as the gate delay or many times more, further eating into timing budgets and limiting the clock speed. However, 1 mm wires, considered long wires, consist of less than 1% of the total interconnects distribution. But global interconnects have even higher aspect ratios (around 2.0 to 2.4) so cross talk still dominates the capacitance. For a chip with number of gates Ng, equal to 1 million, this is roughly 4 million transistors for 2007 32 nm technology, roughly a 2.7 mm2 sized chip, and with very limited functionality. The cumulative interconnect length distribution density shows that interconnects less than 10 μm compose 98% of the interconnects on a chip with 1 million gates.
However with higher RC delay, it means more current (charge) would be needed to charge and discharge (switch) the circuit. Chip designers could use larger transistors to provide more driving current but instead they add more repeaters which are basically inverters on the interconnect line. Adding repeaters adds a little bit of delay but adds current to the signal line because of the pull-up and pull-down structure of CMOS logic.
Repeaters are merely inverters placed in the timing path to manage clock skew due to varying lengths of the paths. Repeaters are not flip-flops that are clock gated, but merely adjust the skew on data path by a few picoseconds, so that data or clocks arrive at all of the load gates/flip-flops at the same time. By splitting up the wire segments into shorter lengths, the RC delay due to the interconnects is managed. However RC delay is not affected significantly by capacitance reduction, but resistance contributes to the majority of the RC delay and capacitance reduction for using low-k materials mitigates the rising resistance.
The crux of the matter is that RC delay has not decreased at all with the lowering of capacitance because of the higher growth rate of resistance. Also with scaling of interconnect widths, the interconnect lengths have not scaled much because IC chip designers have just added more gates and more functions. Resistance is also not scaling linearly anymore due to added effects of surface scattering and line-edge roughness and copper barrier metal thicknesses, which all complicates the linear dependence of R=ρI/A.
Therefore it is not possible to get rid of repeaters by using air-gap technology since resistance is the major contributor to the RC delay. However repeaters will not solve the issue of long-lines running into transmission line effects as although repeaters lessen delay, they are not clocked elements. Therefore IC chip designers have tried to design digital circuits that do not need to travel far distances like multi-core architectures.
Most effort in terms of repeaters has been put to maximize the decision algorithms on how many repeaters should be to put on an interconnect line so that the power penalty due to the repeaters will not be significant.
Each buffer uses power to operate, and increases the total time the signal takes to move along the wire because the signal is “held up” a small amount of time at each buffer. There are a few different methods currently attempting to battle the problem of interconnect speed and power consumption, usually by reducing the number of buffers needed along a signal line. All of the current methods suffer from significant drawbacks.
One current method of reducing the number of buffers is to use a low-k dielectric material as the layer between the metal interconnects, instead of the standard SiO2. As a signal moves along a wire, some of its power is lost to the surrounding dielectric material. A lower dielectric constant means that less power is lost to the surrounding material, meaning fewer buffers are needed to strengthen the signal. However, the low-K dielectric materials require using many types of barriers which increases fabrication costs, and low-k materials also tend to be more porous and poor heat conductors.
One method that had been explored to reduce signal line capacitance is differential signaling. With differential signaling, a signal is placed on one line and simultaneously duplicated but opposite voltage on the other line. Then at the receiver end, the voltage is subtracted and the difference is read to give the signal again. This makes differential signaling less sensitive to noise than single-ended lines. Though the noise margin is doubled and ground offsets are also do not matter because of the subtracting operation that happens at the receiver. Also with differential signaltng lower signal swing is also needed because the receiver looks at the difference in voltages, which will need lower supply voltages to be used.
Also with differential signaling, since typically the two lines are balanced (meaning they have the same impedance to ground), it is less susceptible to electromagnetic interference, and inductive coupling. Differential lines have much more noise immunity because of the differencing at the receiver and since both lines are affected by about the same inductive coupling, then there is little difference between the two signals and the signal is transmitted cleanly.
Having two lines also has the advantage of supplying a nearby return path for every signal, so noise and signals are more isolated from each other and not coupled into nearby signals. Also it becomes more isolated from supply lines and the associated noise of supply lines.
Since the voltages are equal and opposite, the capacitance is constant, and is lower than parallel single-ended lines, where the Miller effect doubles cross-capacitance. Differential lines also have predictable and constant cross-capacitance in between the lines, compared to data-dependent cross-capacitance single-ended lines in CMOS. As a result of higher noise resistance and lower capacitance of differential lines, differential lines can typically have much faster speeds than single-ended lines. However, capacitance can also come from other differential lines or single-ended lines near the differential lines and can be.
However, for CMOS differential lines they will add an extra penalty of two times the number of nets that need to be routed, meaning that 2*N (where N is the number of lines) routing lines will now have to be routed in the same space. Also at each gate, the drivers will have to be modified to also provide the differential signal and receivers will also have to be placed to take the differences in the voltage to get the signal out again for the logic. To determine if all signal lines are to be replaced with differential lines or only some will also require much more design management. Clock jitter and clock skew could still significantly affect differential signal lines.
As with all differential signal schemes, there is always current flowing through one of the lines, so there is a higher static power consumption, compared to CMOS, which only dissipates power in a 1 to 0 transition. Static power consumption of differential signal lines will depend on what the load resistance is on the receiver and resistance of the wire. LVDS uses a common mode voltage of 1.2V which can be driven by CMOS circuits with VDD of 2.5V or lower. Static power consumption across the load resistor on LVDS is 1.2 mW and the low differential voltage, 350 mV, decreases the dynamic power consumption.
Differential signaling has been applied widely off-chip and quite a few standards exist for them. Most of them are high-voltage schemes with the exception of LVDS which uses low-voltage. However, off-chip they can travel quite far distances and at high speeds. Current standards include: LVDS, differential ECL, PECL, LVPECL, RS-422, RS-485, Ethernet physical layers, PCI Express, USB, serial ATA, TMDS, FireWire and HDMI.
Currently on-chip there has been no use of differential signaling, although there have been several designs and several patents. It seems there are many ways to design CMOS circuits to provide differential signals, like the one disclosed in U.S. Pat. No. 6,294,933 which is a fairly simple circuit for the driver, with feed forward capacitors, a receiver, and uses VDD as the reference voltage instead of requiring an outside reference voltage. Using the sizing of transistors, it is possible to make a source drain resistance that will make the signal swing around VDD/2, and with a signal swing of less than ¼ VDD.
It seems differential signaling would be most useful on clock nets which are most active and have highest frequency. Most of the power is saved from the reduction of the signal swing to less than half of the supply voltage. A differential circuit has some static power consumption due to some current always being on the line flowing through the open transistor, even if no signal is being transmitted, the logic state for one line is zero and the other is one. But, at higher frequencies, the total power consumption is less than total power consumption of single ended lines because of the massive reduction in the signal swing voltage (to 25% of the original VDD).
There has been much interest in developing side-air gaps and several papers have been published and it has been mentioned as a possible technology for the future roadmap by ITRS. However, side air-gap technology also poses some integration issues with via mis-alignment leading to chip failure, and also the use of extra masks to limit the air-gaps and integration of new materials like polymers as sacrificial materials as they will modify the copper dual-damascene process.
Another method that is being explored to increase interconnect speed is using optical signals in part, instead of only metal transmission lines. Optical signals are already used in the off-chip case, but on-chip placement faces significant challenges and drawbacks. Primarily, adding optics makes a chip far more complex, and increases difficulty of manufacture and manufacturing cost, it also greatly increases the power needed for the interconnect system.
One example of an on-chip optical interconnect is disclosed in the U.S. Pat. No. 6,147,366. For an optical interconnect, it is necessary to provide a transmitter and a receiver, preferably located on-chip. Silicon can not be used as an emitter, so the emitter must be formed of some other material, or in some cases the light is provided off chip. Then an optical interconnect requires wave guides, guiding the optical signal to its receiver, which further increase the complexity of the chip. Finally by adding the receiver, the overall complexity of the chip is very significantly increased over having a simple metal wire transmit the signal. Both the transmitter and receiver also require power to operate, which is a major drawback compared to a wire which requires little or no power to transmit a signal.